Projects - Lock-In Amplifier - EdsCave

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Projects - Lock-In Amplifier


11 Dec 2017

After writing a series of articles about synchronous detection, I thought it might be interesting to design & build a close cousing - the Lock-In Amplifier, or LIA. Lock-in's are widely used in the physics and signal processing worlds to recover tiny signals from sensors and other sources.  The big difference between the synchronous amplifier, and the LIAs is that while the synchonous detector expects a nice clean reference signal with the appropriate amplitude, duty cycle, and phase realtionship (to the signal to be recovered), an LIA adds a phase-locked loop (PLL) to take whatever referecne signal is available, and generate a nice clean demodulation signal from that.  A block diagram of a typical LIA, such as the one I am tinkering with is shown below.

In the above schematic, you can see the typical synchronous detector functions - pre-amp, demod(ulator), output filter and output amplifier. In addition to these are the pahse locked loop - which locks onto the reference signal, and a phase shifter, which allows you to arbitrarily adjust the phase relationship between the input signal and the regenerated reference signal coming out of the PLL.

For the PLL, I used a 74HC4046-type device with the edge-triggered phase detector.  This circuit likes square waves as inputs, so I added a discriminator circuit (not shown) between the referecne input and the input to the PLL. This additonal circuit allows you to lock onto signals with a wide range of amplitudes and wavefors (like sine waves, triangles, etc..).  While you might think that an analog circuit would be a slam-dunk for the phase shifter, I actually did this digitally. By running the VCO at 16X the reference frequency, and using binary dividers, I implmented a digital phase shifter that lets you shift the demodulator reference waveform in precise 22.5 degree increments - while also assuring a 50% duty ccycle regardless of what gets fed in.  This demodulator reference, as well as an analog monitor of the amplified input signal  are brought out to BNC connectors to make it easy to tune the optimal phase shift.

Below is a pic of the mostly-finished board. The PLL still needs a bit of component selection work to get a wide range of operating frequencies. Some of the key I/O features are:

1) + and - inputs (top left BNCs)
2) +5V power (terminal block on left)
3) REF-IN - the input for the reference (lower left BNC)
4) REF OUT - locked, 50%, phase shifted demodulator signal (lower right BNC)
5) Output - center right BNC
6) Monitor Out - upper right BNC

One thing you may notice is that the board has a lot of dipswitches. The 8-up one in the lower left selects PLL center frequency and loop filter. The 4-up on the lower left controls the digital phase shifter. Two other dip switches control preamp gain, the output filter time constant, and the output amp gain.

So how does it work? The three scope shots below show the amplifier in a locked state with zero, ~200uV and 570uV peak-peak input signals. The yellow trace is a sine wave coming out of the signal generator - the sig-gen's reference output is being fed into the LIA's reference input. The signal generator's sine wave output was then divided down by 1000:1 and fed into the positive input, with the LIA's negative input grounded.  The green fuzz behind the yellow trace is the monitor output, which is the input signal amplified by 1000X. The purple trace is the regenerated and 'locked-in' reference signal which is used to perform the demodulation. Finally, the blue trace on the bottom is the LIA's filtered output. In the 'no signal' case below, you can see that the output is 6.57mV.

When crank the sig-gen to 178mV (178uV input), we can also see the amplified sine wave with additional noise in the monitor output, and 14.3mV on the output.

Cranking the sig-gen even higher to 568mV (568uV input), we can also see a larger amplified fuzzy sine wave  and 36.8mV of output.

The monitor output seems a bit noisy, and originally I thought that the reason was that there was feedthrough from the 16X VCO used in the PLL circuit. A little further investigation showed that a lot of the noise was from the little +5V -> +/-15V DC-DC converter I used to power the analog circuit. In the next rev I should put an option for powering from +/-15V external (linear) supplies, or get a bit more aggressive about filtering the DC-DC's output. Despite the injected noise power-supply, the output is pretty stable, which is something you expect from LIAs in general.

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